Unification of Register Allocation and Instruction Scheduling in Compilers for Fine-grain Parallel Architectures

The i n teraction between instruction scheduling a n d register allocation has signiicant impact on the quality o f c o d e generated, particularly in compilers targeting g n e grain parallel architectures. The problem results from the fact that instruction scheduling a n d register allocation have connicting goals. Instruction scheduling tries to m aximize parallelism by s c heduling a s m any instructions as possible in parallel, which requires a large number of values to b e h eld in registers for short periods of time. On the o t her hand, register allocation attempts t o h old a small numb e r o f v alues in registers for long periods of time, resulting in limiting t he n umber of instructions that can be scheduled in parallel. This dissertation presents a m ethod for unifying t hese tasks by allocating all needed registers and f u nctional units t o an instruction simultaneously. No previous technique has achieved this degree of integration between the t wo t asks. The w ork i n t his dissertation is based on a framework consisting of three components: a technique for measuring a program's demand for all resources, a single intermediate representation of the m easured demands, and a set of transformations that perform resource allocation. The a p proach t aken in this work is based on a new paradigm of resource allocation, called Measure and Reduce in which t he resource requirements o f t he program are measured and excessive demands are removed by r e d uction transformations. The information computed during t he m eas-urement o f t he d emands for each resource is incorporated into a s i n gle intermediate representation. The r e d uction transformations for all resources operate o n t his intermediate representation, allowing transformations for diierent t ypes of resources to be performed simultaneously. T h erefore, an instruction can be allocated all resources it needs at once, resulting i n u niied resource allocation. The i n termediate representation is based on a hierarchical form of dependence DAGs, enabling t he transformations to n aturally handle instruction level parallelism. In particular, the register transformations form a framework for live range splitting i n t he a bsence of a full ordering o f t he instructions, as required by previous splitting …